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this is information on a product in full production. august 2012 doc id 16891 rev 27 1/42 1 m24c64-w m24c64-r M24C64-F m24c64-df 64-kbit serial i2c bus eeprom datasheet ? production data features compatible with all i 2 c bus modes: ?1 mhz ? 400 khz ? 100 khz memory array: ? 64 kbit (8 kbytes) of eeprom ? page size: 32 bytes ? additional write lockable page (m24c64-d order codes) single supply voltage: ? 1.7 v to 5.5 v over ?40 c / +85 c write: ? byte write within 5 ms ? page write within 5 ms random and sequential read modes write protect of the whole memory array enhanced esd/latch-up protection more than 4 million write cycles more than 200-year data retention packages: ? rohs compliant and halogen-free (ecopack ? ) pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mc) wlcsp (cs) thin wlcsp (ct) preliminary data www.st.com
contents m24c64-w m24c64-r M24C64-F m24c64-df 2/42 doc id 16891 rev 27 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2, e1, e0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 write identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 lock identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 18 5.1.6 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 19 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m24c64-w m24c64-r M24C64-F m24c64-df contents doc id 16891 rev 27 3/42 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 read identification page (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 read the lock status (m24c64-d only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
list of tables m24c64-w m24c64-r M24C64-F m24c64-df 4/42 doc id 16891 rev 27 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. operating conditions (voltage range f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. dc characteristics (m24c64-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. dc characteristics (m24c64-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. dc characteristics (M24C64-F, m24c64-df, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 28 table 16. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33 table 19. so8n ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 34 table 20. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 35 table 21. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22. wlcsp-r 5-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . . 37 table 23. thin wlcsp 8-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . 38 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
m24c64-w m24c64-r M24C64-F m24c64-df list of figures doc id 16891 rev 27 5/42 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. 5-bump wlcsp connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. 8-bump thin wlcsp connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33 figure 17. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34 figure 18. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 35 figure 19. ufdfpn8 (mlp8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . 36 figure 20. wlcsp-r 5-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21. thin wlcsp 8-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . 38
description m24c64-w m24c64-r M24C64-F m24c64-df 6/42 doc id 16891 rev 27 1 description the m24c64 is a 64-kbit i 2 c-compatible eeprom (electrica lly erasable programmable memory) organized as 8 k 8 bits. the m24c64-w can operate with a supply voltage from 2.5 v to 5.5 v, the m24c64-r can operate with a supply voltage from 1.8 v to 5.5 v, and the M24C64-F and m24c64-df can operate with a supply voltage from 1.7 v to 5.5 v, over an ambient temperature range of -40 c / +85 c. the m24c64-d offers an additional page, named the identification page (32 bytes). the identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram figure 2. 8-pin package connections 1. see section 9: package mechanical data for package dimensions, and how to identify pin 1. table 1. signal names signal name function direction e2, e1, e0 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage v ss ground !)f % % 3$! 6 ## -xxx 7# 3#, 6 33 3$! 6 33 3#, 7# % % 6 ## % !)f
m24c64-w m24c64-r M24C64-F m24c64-df description doc id 16891 rev 27 7/42 figure 3. 5-bump wlcsp connections (top view) note: inputs e2, e1, e0 are internally connected to (001). please refer to section 2.3 for further explanations. figure 4. 8-bump thin wlcsp connections (top view) caution: as eeprom cells lose their charge (and so their binary value) when exposed to ultra violet (uv) light, eeprom dice delivered in wafer form or in wlcsp package by stmicroelectronics must never be exposed to uv light. -36 6 ## 6 33 3$! 7# 3#, -36 7# 6## % 3$! % 3#, 633 %
signal description m24c64-w m24c64-r M24C64-F m24c64-df 8/42 doc id 16891 rev 27 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be connected from serial data (sda) to v cc ( figure 13 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2, e1, e0) (e2,e1,e0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see ta bl e 2 ). these inputs must be tied to v cc or v ss , as shown in figure 5 . when not connected (left floating), these inputs are read as low (0). for the 5-balls wlcsp package, the (e2,e1,e0) inputs are internally connected to (0,0,1). figure 5. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disabled to the entire memory array when write control (wc ) is driven high. write operations are enabled when write control (wc ) is either driven low or left floating. when write control (wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
m24c64-w m24c64-r M24C64-F m24c64-df signal description doc id 16891 rev 27 9/42 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters) . in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop cond ition, assuming that there is no internal write cycle in progress).
memory organization m24c64-w m24c64-r M24C64-F m24c64-df 10/42 doc id 16891 rev 27 3 memory organization the memory is organized as shown below. figure 6. block diagram -36 7# #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder )dentificationpage % % 3#, 3$! %
m24c64-w m24c64-r M24C64-F m24c64-df device operation doc id 16891 rev 27 11/42 4 device operation the device supports the i 2 c protocol. this is summarized in figure 7 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 7. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
device operation m24c64-w m24c64-r M24C64-F m24c64-df 12/42 doc id 16891 rev 27 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer instruction. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is fo llowed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
m24c64-w m24c64-r M24C64-F m24c64-df device operation doc id 16891 rev 27 13/42 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). when the device select code is received, the device only responds if the chip enable address is the same as the value on its chip enable e2,e1,e0 inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, the device deselects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2)(3) 2. e0, e1 and e2 are compared with the value read on input pins e0,e1,and e2. 3. for the 5-bump wlcsp package, (e0,e1,e2) i nputs are internally connected to (0,0,1) rw b7 b6 b5 b4 b3 b2 b1 b0 device select code when addressing the memory array 1010e2e1e0rw device select code when accessing the identification page 1011e2e1e0rw
instructions m24c64-w m24c64-r M24C64-F m24c64-df 14/42 doc id 16891 rev 27 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/w bit (rw ) reset to 0. the device acknowledges this, as shown in figure 8 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (sda) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 9 . table 3. most significant address byte a15 a14 a13 a12 a11 a10 a9 a8 table 4. least significant address byte a7 a6 a5 a4 a3 a2 a1 a0
m24c64-w m24c64-r M24C64-F m24c64-df instructions doc id 16891 rev 27 15/42 5.1.1 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected, by write control (wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 8 . figure 8. write mode sequences with wc = 0 (data write enabled) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01106d page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack
instructions m24c64-w m24c64-r M24C64-F m24c64-df 16/42 doc id 16891 rev 27 5.1.2 page write the page write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a15/a5, are the same. if mo re bytes are sent than will fit up to the end of the page, a ?roll-over? occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if write control (wc ) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack, as shown in figure 9 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bus master generating a stop condition. figure 9. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev sel byte addr byte addr data in wc start page write dev sel byte addr byte addr data in 1 wc data in 2 ai01120d page write (cont'd) wc (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
m24c64-w m24c64-r M24C64-F m24c64-df instructions doc id 16891 rev 27 17/42 5.1.3 write identificati on page (m24c64-d only) the identification page (32 bytes) is an addi tional page which can be written and (later) permanently locked in read-only mode. it is written by issuing the write identification page instruction. this instruction uses the same protocol and format as page write (into memory array), except for the following differences: device type identifier = 1011b msb address bits a15/a5 are don't care except for address bit a10 which must be ?0?. lsb address bits a4/a0 define the byte address inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 5.1.4 lock identification page (m24c64-d only) the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is similar to byte write (into memory array) with the following specific conditions: device type identifier = 1011b address bit a10 must be ?1?; all other address bits are don't care the data byte must be equal to the binary value xxxx xx1x, where x is don't care
instructions m24c64-w m24c64-r M24C64-F m24c64-df 18/42 doc id 16891 rev 27 5.1.5 ecc (error correction code) and write cycling the error correction code (ecc) is an internal logic function which is transparent for the i 2 c communication protocol. the ecc logic is implemented on each group of four eeprom bytes (a) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on groups of four bytes, a single byte can be written/cycled independently. in this case, the ecc function also writes/cycles the three other bytes located in the same group (a) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined table 11: cycling performance by groups of four bytes . a. a group of four bytes is located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
m24c64-w m24c64-r M24C64-F m24c64-df instructions doc id 16891 rev 27 19/42 5.1.6 minimizing write del ays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 10 , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 10. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure). write cycle in progress ai 01847 d ai01847e next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write cperation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no startcondition continue the write operation continue the random read operation
instructions m24c64-w m24c64-r M24C64-F m24c64-df 20/42 doc id 16891 rev 27 5.2 read operations read operations are performed independently of the state of the write control (wc ) signal. after the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode. figure 11. read mode sequences 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 11 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. start dev sel * byte addr byte addr start dev sel data out 1 ai01105d data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr byte addr sequention random read start dev sel * data out1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
m24c64-w m24c64-r M24C64-F m24c64-df instructions doc id 16891 rev 27 21/42 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/w bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 11 , without acknowledging the byte. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 11 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.3 read identification page (m24c64-d only) the identification page (32 bytes) is an addi tional page which can be written and (later) permanently locked in read-only mode. the identification page can be read by issuing an read identification page instruction. this instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. the msb address bits a15/a5 are don't care, the lsb address bits a4/a0 define the byte address inside the identification page. the number of bytes to read in the id page must not exceed the page boundary (e.g.: when reading the identification page from location 10d, the number of bytes should be less than or equal to 22, as the id page boundary is 32 bytes). 5.4 read the lock status (m24c64-d only) the locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. the device returns an acknowledge bit if the identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: start: the truncated command is not executed because the start condition resets the device internal logic, stop: the device is then set back into standby mode by the stop condition.
initial delivery state m24c64-w m24c64-r M24C64-F m24c64-df 22/42 doc id 16891 rev 27 6 initial delivery state the device is delivered with all the memory array bits set to 1 (each byte contains ffh).
m24c64-w m24c64-r M24C64-F m24c64-df maximum rating doc id 16891 rev 27 23/42 7 maximum rating stressing the device outside the ratings listed in ta bl e 5 may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std- 020d (for small body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c pdip-specific lead temperature during soldering 260 (2) 2. t lead max must not be applied for more than 10 s. c v io input or output range ?0.50 6.5 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (3) 3. positive and negative pulses applied on different comb inations of pin connect ions, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 ). -4000v
dc and ac parameters m24c64-w m24c64-r M24C64-F m24c64-df 24/42 doc id 16891 rev 27 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. table 6. operating conditions (voltage range w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 (1) 1. f cmax is 1 mhz devices identified by process letter k. mhz table 7. operating conditions (voltage range r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 (1) 1. f cmax is 1 mhz devices identified by process letter k. mhz table 8. operating conditions (voltage range f) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 1 (1) 1. f cmax is 1 mhz devices identified by process letter k. mhz table 9. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf scl input rise/fall time, sda input fall time 50 ns input levels 0.2 v cc to 0.8 v cc v input and output timing reference levels 0.3 v cc to 0.7 v cc v
m24c64-w m24c64-r M24C64-F m24c64-df dc and ac parameters doc id 16891 rev 27 25/42 figure 12. ac measurement i/o waveform table 10. input parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z l input impedance (e2, e1, e0, wc ) (2) 2. e2, e1, e0 input impedance when the memory is selected (after a start condition). v in < 0.3 v cc 30 k z h v in > 0.7 v cc 500 k table 11. cycling performance by groups of four bytes symbol parameter test condition (1) 1. cycling performance for products identified by process letter k. max. unit ncycle write cycle endurance (2) 2. the write cycle endurance is defined for groups of four data bytes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer. the write cycle endurance is defined by characterization and qualification. ta 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle (3) 3. a write cycle is executed when ei ther a page write, a byte write, a write identification page or a lock identification page instruction is decoded. when usi ng the byte write, the page write or the write identification page, refer also to section 5.1.5: ecc (error corr ection code) and write cycling . ta = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 12. memory cell data retention parameter test co ndition min. unit data retention (1) 1. for products identified by process letter k. the data retention behavior is c hecked in production. the 200- year limit is defined from characterization and qualification results. ta = 55 c 200 year -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
dc and ac parameters m24c64-w m24c64-r M24C64-F m24c64-df 26/42 doc id 16891 rev 27 table 13. dc characteristics (m24c64-w, device grade 6) symbol parameter test conditions (see table 6 )min.max.unit i li input leakage current (scl, sda, e2, e1, e0) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) 2.5 v < v cc < 5.5 v, f c = 400 khz (rise/fall time < 50 ns) 2ma 2.5 v < v cc < 5.5 v, f c = 1 mhz (1) (rise/fall time < 50 ns) 1. only for devices identified with process letter k. 2.5 ma i cc0 supply current (write) during t w , 2.5 v < v cc < 5.5 v 5 (2) 2. characterized value, not tested in production. ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 2.5 v 3. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 2a device not selected (3) , v in = v ss or v cc , v cc = 5.5 v 5 (4) 4. the new m24c64-w devices (identified by the process letter k) offer i cc1 = 3a (max) a v il input low voltage (scl, sda, wc) ?0.45 0.3 v cc v v ih input high voltage (scl, sda) 0.7 v cc 6.5 v input high voltage (wc, e2, e1, e0) 0.7 v cc v cc +0.6 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v 0.4 v
m24c64-w m24c64-r M24C64-F m24c64-df dc and ac parameters doc id 16891 rev 27 27/42 table 14. dc characteristics (m24c64-r, device grade 6) symbol parameter test conditions (1) (in addition to those in table 7 ) 1. if the application uses the voltage range r device with 2.5 v < v cc < 5.5 v and -40 c < ta < +85 c, please refer to table 13 instead of this table. min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.8 v, f c = 400 khz 0.8 ma f c = 1 mhz (2) 2. only for devices identified with process letter k. 2.5 ma i cc0 supply current (write) during t w 1.8 v < v cc < 2.5 v 3 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.8 v 4. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 1a v il input low voltage (scl, sda, wc) 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) 1.8 v v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc) 1.8 v v cc < 2.5 v 0.75 v cc v cc +0.6 v v ol output low voltage i ol = 1 ma, v cc = 1.8 v 0.2 v
dc and ac parameters m24c64-w m24c64-r M24C64-F m24c64-df 28/42 doc id 16891 rev 27 . table 15. dc characteristics (M24C64-F, m24c64-df, device grade 6) symbol parameter test conditions (1) (in addition to those in table 8 ) 1. if the application uses the voltage range f device with 2.5 v < v cc < 5.5 v and -40 c < ta < +85 c, please refer to table 13 instead of this table. min. max. unit i li input leakage current (e1, e2, scl, sda) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc = 1.7 v, f c = 400 khz 0.8 ma f c = 1 mhz (2) 2. only for devices identified with process letter k. 2.5 ma i cc0 supply current (write) during t w 1.7 v < v cc < 2.5 v 3 (3) 3. characterized value, not tested in production. ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc = 1.7 v 4. the device is not selected after power-up, after a r ead instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 1a v il input low voltage (scl, sda, wc) 1.7 v v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) 1.7 v v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc, e2, e1, e0) 1.7 v v cc < 2.5 v 0.75 v cc v cc +0.6 v v ol output low voltage i ol = 1 ma, v cc = 1.7 v 0.2 v
m24c64-w m24c64-r M24C64-F m24c64-df dc and ac parameters doc id 16891 rev 27 29/42 table 16. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 300 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 (5) 5. the previous product iden tified by process letter p was specified with t clqx = 200 ns (min). both values offer a safe margin compared to the i 2 c specification recommendations. -ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is within the values specified in figure 13 . t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t wldl (7)(1) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8)(1) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr internal write cycle duration - 5 ms t ns (1) pulse width ignored (input filter on scl and sda) - single glitch -80 (9) 9. the previous m24c64 device (identifi ed by process letter p) offers t ns = 100 ns (max), while the current m24c64 device offers t ns = 80 ns (max). both products offer a safe margin compared to the 50 ns minimum value recommended by the i 2 c specification. ns
dc and ac parameters m24c64-w m24c64-r M24C64-F m24c64-df 30/42 doc id 16891 rev 27 table 17. 1 mhz ac characteristics symbol alt. parameter (1) 1. only for m24c64 devices ident ified by the process letter k. min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 500 - ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal ri se and fall times be less than 120 ns when f c <1mhz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t ql1ql2 (3) 3. characterized only, not tested in production. t f sda (out) fall time 20 (4) 4. with c l = 10 pf. 120 ns t dxcx t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (5) 5. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time consta nt is within the values specified in figure 14 . t aa clock low to next data valid (access time) 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t wldl (7)(3) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8)(3) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 5 ms t ns (3) pulse width ignored (input filter on scl and sda) -80ns
m24c64-w m24c64-r M24C64-F m24c64-df dc and ac parameters doc id 16891 rev 27 31/42 figure 13. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 14. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
dc and ac parameters m24c64-w m24c64-r M24C64-F m24c64-df 32/42 doc id 16891 rev 27 figure 15. ac waveforms 3#, 3$!/ut 3#, 3$!)n $atavalid t#,16 t#,18 t#($( 3top condition t#($, 3tart condition 7ritecycle t7 !)g $atavalid t1,1, 3$!)n t#($, 3tart condition t$8#( t#,$8 3$! )nput 3$! #hange t#($( t$($, 3top condition 3tart condition t8(8( 3#, t#(#, t$,#, t#,#( t8(8( t8,8, t8,8, 7# t7,$, t$(7(
m24c64-w m24c64-r M24C64-F m24c64-df package mechanical data doc id 16891 rev 27 33/42 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 16. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8
package mechanical data m24c64-w m24c64-r M24C64-F m24c64-df 34/42 doc id 16891 rev 27 figure 17. so8n ? 8 lead plastic small outli ne, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8n ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 1.750 0.0689 a1 0.100 0.250 0.0039 0.0098 a2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 ccc 0.100 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 k 08 08 l 0.400 1.270 0.0157 0.0500 l1 1.040 0.0409 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
m24c64-w m24c64-r M24C64-F m24c64-df package mechanical data doc id 16891 rev 27 35/42 figure 18. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package outline 1. drawing is not to scale. table 20. pdip8 ? 8 pin plastic dip, 0.25 mm lead frame, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ. min. max. typ. min. max. a 5.33 0.2098 a1 0.38 0.0150 a2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.20 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.3650 0.3551 0.4000 e 7.87 7.62 8.26 0.3098 0.3000 0.3252 e1 6.35 6.10 7.11 0.2500 0.2402 0.2799 e2.54? ?0.1000? ? ea 7.62 ? ? 0.3000 ? ? eb 10.92 0.4299 l 3.30 2.92 3.81 0.1299 0.1150 0.1500 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package mechanical data m24c64-w m24c64-r M24C64-F m24c64-df 36/42 doc id 16891 rev 27 figure 19. ufdfpn8 (mlp8) - 8-lead ultra thin fine pitch dual flat no lead, package outline 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) is in ternally pulled to v ss . it must not be connected to any other voltage or signal line on the pcb, for example during the soldering process. table 21. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) 1.200 1.600 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) 1.200 1.600 0.0472 0.0630 e 0.500 0.0197 k (rev mc) 0.300 0.0118 l 0.300 0.500 0.0118 0.0197 l1 0.150 0.0059 l3 0.300 0.0118 eee (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. 0.080 0.0031 $ % :7?-%e6 ! ! eee , e b $ , % , 0in +
m24c64-w m24c64-r M24C64-F m24c64-df package mechanical data doc id 16891 rev 27 37/42 figure 20. wlcsp-r 5-bump wafer-length chip-scale package outline 1. drawing is not to scale. 2. the index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). table 22. wlcsp-r 5-bump wafer-length chip-scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.545 0.490 0.600 0.0215 0.0193 0.0236 a1 0.190 0.0075 a2 0.355 0.0140 b (2) 2. dimension measured at the maximum bump diameter parallel to primary datum z. 0.270 0.0106 d 0.959 1.074 0.0378 0.0423 e 1.073 1.168 0.0422 0.0460 e 0.693 0.0273 e1 0.400 0.0157 e2 0.3465 0.0136 f 0.280 0.0110 g 0.190 0.0075 aaa 0.110 0.0043 eee 0.060 0.0024 "ump $etail! rotatedby? 7aferbackside 3ideview $etail! "umpside ! ! e e e # " ! ' & ! $ % b -36 )ndex )ndex
package mechanical data m24c64-w m24c64-r M24C64-F m24c64-df 38/42 doc id 16891 rev 27 figure 21. thin wlcsp 8-bump wafer-length chip-scale package outline 1. drawing is not to scale. 2. the index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). table 23. thin wlcsp 8-bump wafer-length chip-scale package mechanical data (1) 1. these data are preliminary. symbol millimeters inches (2) 2. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.315 0.300 0.330 0.0124 0.0118 0.0130 a1 0.115 0.0045 a2 0.200 0.0079 b (3) 3. dimension measured at the maximum bump diameter parallel to primary datum z. 0.160 0.0063 d 1.073 1.093 0.0422 0.0430 e 0.959 0.979 0.0378 0.0385 e 0.693 0.0273 e1 0.800 0.0315 e2 0.400 0.0157 f 0.133 0.0052 g 0.137 0.00524 aaa 0.110 0.0043 eee 0.060 0.0043 8 aaa 7aferbackside $ % 3ideview $etail! ! ! e e e ' & "umpsside & $etail! 2otated? "ump eee 3eatingplane #i?-%?6 e b 8 9 : : 2eference /rientation reference ( !
m24c64-w m24c64-r M24C64-F m24c64-df part numbering doc id 16891 rev 27 39/42 10 part numbering table 24. ordering information scheme example: m24c64 - d w mn 6 t p /p device type m24 = i 2 c serial access eeprom device function c64 = 64 kbit (8192 x 8) device family blank: without identification page d: with additional identification page operating voltage w = v cc = 2.5 v to 5.5 v r = v cc = 1.8 v to 5.5 v f = v cc = 1.7 v to 5.5 v package bn = pdip8 (1) 1. rohs-compliant (ecopack1 ? ) mn = so8 (150 mil width) (2) 2. rohs-compliant and halogen-free (ecopack2 ? ) dw = tssop8 (169 mil width) (2) mc = ufdfpn8 (mlp8) (2) cs = 5-bump wlcsp (2) ct = 8-bump thin wlcsp (2) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant) process (3) 3. the process letters appear on the device package (marking) and on the shipment box. please contact your nearest st sales office for further information. /p or /k = manufacturing technology code
revision history m24c64-w m24c64-r M24C64-F m24c64-df 40/42 doc id 16891 rev 27 11 revision history table 25. document revision history date revision changes 14-mar-2011 22 updated information concerning e2, e1, e0 for the wlcsp package: ? note under figure 3: 5-bump wlcsp connections (top view) ? comment under figure 5: device select code ? note 3 under table 2: device select code 07-apr-2011 23 updated mlp8 package data and section 10: part numbering . added footnote (a) in section 4.5: memory addressing . 18-may-2011 24 updated: ? figure 3: 5-bump wlcsp connections (top view) ? table 5: absolute maximum ratings ? small text changes added: ? figure 12: memory cell characteristics 08-sep-2011 25 updated: ? table 21: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data ? figure 14: maximum rbus value versus bus parasitic capacitance cbus) for an i2c bus at maximum frequency fc = 1mhz ? figure 6: i 2 c fast mode plus (f c = 1 mhz): maximum r bus value versus bus parasitic capacitance (c bus ) . added t wldl and t dhwh in: ? table 16: 400 khz ac characteristics ? table 17: 1 mhz ac characteristics ? figure : minor text changes.
m24c64-w m24c64-r M24C64-F m24c64-df revision history doc id 16891 rev 27 41/42 16-dec-2011 26 updated a dimension in table 22: wlcsp-r 5-bump wafer-length chip- scale package mechanical data . 28-aug-2012 27 datasheet split into: ? m24c64-df, m24c64-w, m24c64-r, M24C64-F (this datasheet) for tandard products (range 6), ? m24c64-125 datasheet for automotive products (range 3). added 8-bump thin wlcsp. updated single supply voltage and nu mber of write cycles on cover page. updated section 2.1: serial clock (scl) and section 2.2: serial data (sda) . updated figure 6: block diagram . added section 4.5: device addressing . section 5.1: write operations move to section 5: instructions and updated. moved figure 8: write mode sequences with wc = 0 (data write enabled) to section 5.1.1: byte write . section 5.1.2: page write : changed address bits to a15/a5 and updated figure 9 . case of locked write identification page removed from section 5.1.4: lock identification page (m24c64-d only) . updated section 5.1.5: ecc (error correction code) and write cycling and move figure 10: write cycle pollin g flowchart using ack to section 5.1.6: minimizing write delays by polling on ack . added note 1 in table 6: operating conditions (voltage range w) and table 7: operating conditions (voltage range r) . added table 11: cycling performance by groups of four bytes and updated table 12: memory cell data retention . removed note 2 in table 16: 400 khz ac characteristics for t ql1ql2, t wldl, t dhwh, and t ns. table 24: ordering information scheme : removed ambient operating temperature for device grade 5 and added note 2. to mlp8 and wlcsp packages. table 25. document revision history (continued) date revision changes
m24c64-w m24c64-r M24C64-F m24c64-df 42/42 doc id 16891 rev 27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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